1. Field of the Invention
The invention relates to the field of differential switches and, in particular, to differential switches operated under control of a single binary signal, as in the case of digital to analog converters (DACs).
2. Description of the Related Art
Binary-control differential switches operate as single-pole double-throw switches and are employed in many applications such as DACs. Within such a switch, a single control terminal effects contact between a first conducting terminal and a second conducting terminal while breaking contact between the first conducting terminal and a third conducting terminal. Although the utility of such switches will be described in reference to their application within DACs, they may be used for many other applications.
There are a number of conventional DAC architectures which employ differential switches. Some are current output, some are voltage output. For examples of both see, Analog-Digital Conversion Handbook, Daniel H. Sheingold ed., Prentice Hall, Englewood Cliffs, N.J., 1986, pages 191-206. A current output DAC is illustrated in FIG. 1, but the new switches are applicable to voltage output DACs as well. Generally, a DAC is a device which converts a quantity specified as a binary number (this includes BCD, two""s complement and other binary codes) into a current or voltage which is proportional to the value of the digital input. The digital input is typically held in a digital section 11 which may receive the digital input either serially or in parallel through a digital interface 13. The binary number thus stored typically controls an analog output section 15 which comprises a set of differential switches S1-Sn, with each bit of the binary number controlling which one of two terminals within an associated differential switch S1-Sn is connected to a third terminal within the switch. In some cases a single switch is employed to xe2x80x9cbuild upxe2x80x9d an analog signal over some period of time.
More specifically, in the design of FIG. 1, an array of differential switches S1-Sn connect binarily-weighted current sources I1-In to either a return, or reference, terminal 10 or output terminal 12 under control, respectively, of binary control inputs from the least significant bit LSB 14 to the most significant bit MSB 18. Current for the sources I1-In is provided through terminal 9. The sum of the currents appearing at the output terminal 12 provide a xe2x80x9cstair stepxe2x80x9d approximation to the continuous signal represented by the binary control inputs MSB-LSB. Alternatively, the reference terminal 10 and output terminal 12 could be connected to high and low voltage references and the terminal 9 would then provide a voltage output. In this case, the taps of a resistor ladder are connected in place of the current sources I1-In.
As the binary values at the control inputs LSB-MSB vary, the switches S1-Sn route currents corresponding to the varying binary values of the control inputs to the output terminal, where the total current may be converted into a voltage. The switches are generally switched xe2x80x9csimultaneouslyxe2x80x9d to provide valid current levels at the output terminal 12. However, as will be explained in greater detail in relation to FIG. 2, there is often a delay introduced between the xe2x80x9cmakexe2x80x9d and xe2x80x9cbreakxe2x80x9d actions of the switches S1-Sn, causing spurious signals, or xe2x80x9cglitchesxe2x80x9d, to appear at the output terminal 12.
The mid-scale glitch, produced by the transition of the control codes appearing at terminals 18-14 between 1000 . . . 0 and 0111 . . . 1, is usually the worst glitch because all the switches S1-Sn are switching at this transition. Glitches will also occur at other transition points, but they will generally be of lesser magnitude. Glitches are particularly onerous in waveform reconstruction applications such as direct digital synthesis systems.
Code-dependent glitches, such as those just discussed, will produce both out-of-band and in-band harmonics of the desired signal. For example, in reconstructing a sine wave, the midscale glitch occurs twice during each sine wave period, at each mid-scale crossing. In this manner the midscale glitches produce a second harmonic of the sinewave. Although filtering may eliminate or reduce to a tolerable level the contribution from some of the glitches, higher order harmonics, which alias back into the Nyquist bandwidth, cannot be filtered. To avoid filtering and to eliminate spurious signals that cannot be filtered, it would therefore be desirable to avoid introducing the glitches whenever possible.
The block diagram of FIG. 2A provides a more detailed view of a typical conventional switch, which may be employed as one of switches S1-Sn of FIG. 1. As an example, switch S1 includes a differential switch pair 20, comprising switches swa and swb, which connect either terminal a or b to terminal c. Control terminals T and I are connected to receive complementary control signals developed within a latch L1. The latch L1 accepts the binary control signal MSB and converts it into a complementary pair of control signals for use with the differential pair swa and swb. The utility of the latch L1 derives from the fact that, at a system level, whatever device is driving, or controlling, the DAC, in all probability has other duties to perform and may address those other duties only if it stores its required digital patterns within the switches S1-Sn, and then proceeds to other operations.
The control input MSB provides a digital signal path for control inputs to the switch S1. An MSB signal enters the latch L1 and, under control of enable signals ck and ckb, is transferred through an analog switch ASW1. It is then inverted, or complemented, by an inverter INV1 to produce a control signal INVERTED which is applied to the control terminal of the switch swb. Analog switches are known in the art. A description of them may be found in, Paul Horowitz, and Winfield Hill, The Art of Electronics, Cambridge University Press, N. Y., 1989, pages 142-143. The output of the inverter INV1 is connected to the input of a second inverter INV2 which inverts the signal INVERTED to produce a control signal TRUE which is applied to the control input 24 of the switch swb, the other switch of the differential pair. Note that inversion of the INVERTED signal by inverter INV2 produces a delay between the control signals applied to the differential pair. That is, the INVERTED signal will arrive at the control terminal 22 of switch swb one inverter""s delay before the TRUE signal arrives at the control terminal 24 of switch swa. Consequently, a glitch impulse will be created at the S1 output terminal c.
Returning to the operation of the latch L1, the enable signals ck and ckb are assumed to be complementary and non-overlapping. That is, more circuitry than a simple inverter is required to produce ckb from ck. During a first phase of the enable signals ck and ckb, the input signal from MSB is xe2x80x9cclockedxe2x80x9d through the analog switch ASW1. At the same time, because the control inputs to analog switch ASW2 are connected opposite to the connection of ASW1, ASW2 will be xe2x80x9coffxe2x80x9d, thus isolating the output of ASW1 from the output of the inverter INV2.
However, during the second phase of the enable signals, analog switch ASW1 is off and ASW2 is on. With ASW1 off, the MSB terminal is isolated from the circuit beyond the analog switch ASW1. With analog switch ASW2 on, inverters INV1 and INV2 are xe2x80x9ccross-coupledxe2x80x9d. That is, the output of INV1 feeds the input of INV2 and the output of INV2 feeds the input of INV1. In this conventional configuration, there are two stable states which the inverters may assume, i.e., INV1=1, INV2=0 or INV1=0, INV2=1 and, by feedback, they will remain in whichever state to which they are forced. In this way the cross-coupled inverters, coupled through the switches ASW1 and ASW2, form a latch which provides TRUE(delayed) and INVERTED control signals for a differential switch pair from a single binary control signal i.e., that from the MSB terminal.
The switches swa and swb which comprise the differential pair may be any type of switch, including p-channel or n-channel MOSFETs, NPN or PNP bipolar transistor or analog switches. Employing analog switches for switches swa and swb provides some flexibility in choosing between current output or voltage output DACs. An implementation which employs PNP transistors as switches swa and swb is illustrated in FIG. 2B, for example. The emitters of two PNP transistors are connected to a current source such as I1 in FIG. 1 A single control signal, e.g. MSB, is converted to a differential pair of control signals and applied to the respective control terminals 22 and 24, i.e. the bases, of the transistors. With complementary control signals, only one of the transistors will conduct at a given time(ideally), switching current, for example, from the current source I1 into either a return 10 or output 12 path.
An analog switch implementation of the differential switch pair, illustrated in FIG. 2C, operates substantially the same as the PNP transistor pair of FIG. 2B. Differential control signals derived from a control input such as MSB are applied, cross-coupled, to the inverting and non-inverting control inputs of two analog switches. One input, or switch contact, of each analog switch is connected to a current source, the other input is connected to the return terminal 10, the other input of swb is connected to output terminal 12. Ideally, the differential control signals place only one of the switches in the conduction mode at a time, thereby switching current from the current source either into the return path or into the output 12 path. However, as described above, the delay between control signals TRUE and INVERTED sometimes place both switches swa and swb into conduction at the same time.
The advantage of employing analog switches for switches swa and swb lies in the fact that they conduct bidirectionally; therefore a voltage output may be produced by substituting voltage references at the return 10 and output 12 terminals and taking the output from the terminal 14 which, in the current output configuration, provides the reference current I1.
Another latch may be added xe2x80x9cin front ofxe2x80x9d L1 to produce a conventional master/slave latch which provides added isolation between input and output. This additional level of isolation may be used, for example, to update a binary input value by shifting a desired binary value into position at the inputs to a set of master latches, keeping the slave latches isolated, then shifting the updated value into the slave latches simultaneously.
As just described, conventional switches require a somewhat elaborate scheme to produce non-overlapping complementary enable signals to drive the control inputs of analog switches which, along with a pair of inverters, form a binary to differential control latch. Not only is an elaborate enable signal required, glitches, which may create unfilterable spurious signals, are produced by the delay between the generation of TRUE and INVERTED control signals for the differential switch pair.
The invention is directed to a differential switch that minimizes the complexity of a switch controller""s clock generation circuitry and reduces spurious switching, thereby reducing the occurrence and duration of undesirable switch outputs, or glitches. These goals are achieved by a latched differential switch which inverts the control input and then simultaneously transfers the control input and its complement through transfer switches into storage elements. Although inverting the control signal introduces a delay between the control signal and its complement (referred to as the xe2x80x9cTRUExe2x80x9d and xe2x80x9cINVERTEDxe2x80x9d signals hereinafter), simultaneously transferring them into storage elements eliminates this skew. The storage elements"" outputs are connected to the control inputs of a differential switch pair, thus providing xe2x80x9cde-skewedxe2x80x9d control for a differential switch pair from a single binary control input.
In one implementation, the novel switch includes a n intermediate set of transfer switches, operated from the same xe2x80x9cenablexe2x80x9d signal as the first set of transfer switches, and an intermediate set of storage elements. The intermediate sets of switches and storage elements are interposed between the TRUE and INVERTED inputs and the first set of transfer switches. During the first cycle of the enable signal, the TRUE and INVERTED signals are simultaneously transferred into the intermediate set of storage elements. As described above, this simultaneous transfer eliminates the skew between the TRUE and INVERTED signals. The TRUE and INVERTED signals are then transferred into the first storage element, which is isolated from the intermediate storage element, during the second cycle of the enable signal.
The isolation between the first and second storage elements prevents transitions at the input to the second storage element from appearing at the first storage element. The TRUE and INVERTED signals are therefore available from the second storage element without the skew between them that had been introduced by inverting the control signal. The outputs of the first storage element are connected, as described above, to the control inputs of a differential switch pair, thus providing xe2x80x9cde-skewedxe2x80x9d control for the switch pair. The novel switch may be used, for example, within a DAC to reduce the DAC""s glitch energy output.
These and other features, aspects and advantages of the invention will be apparent to those skilled in the art from the following detailed description, take together with the accompanying drawings.